The present invention relates to a semiconductor package of a ultra-many-pin structure in which a semiconductor chip is bonded to a novel lead frame, and to a manufacturing method of the lead frame.
FIG. 1 shows a conventional semiconductor package which can be mounted on a printed wiring board or the like through an organic board having external connection terminals such as solder balls.
As shown in FIG. 1, a semiconductor chip 51 is mounted on the front surface of a multilayered organic wiring board 50 of about 2 to 6 layers which is made of an organic material. Electrode pads of the semiconductor chip 51 are connected to wiring films 52 that are formed on the front surface of the multilayered organic wiring board 50 by wire bonding, i.e., with gold wires 53 or the like.
The back surface of the multilayered organic wiring board 50 is provided with solder balls (external connection terminals) 55 which are electrically connected to the wiring films 52 on the front surface via through-holes 54. The solder balls 55 project from openings of a solder resist film 56. The semiconductor chip 51 is sealed with a sealing resin 57 together with the gold wires 53.
In the above-configured semiconductor package 58, the solder balls 55 formed on the back surface are connected to a printed wiring board 59. In many cases the multilayered organic wiring board 50 is called a ball grind array (BGA) because a number of solder balls 55 are arranged in grid form, and the semiconductor package 58 using the multilayered organic wiring board 50 is called a BGA package.
However, there is a certain limit in reducing the wiring pitch in the conventional semiconductor package 58, because the electrode pads of the semiconductor chip 51 are connected to the wiring films 52 of the multilayered organic wiring board 50 by wire bonding. In the case of a semiconductor package called TCP (tape carrier package), leads are formed by etching metal foil (copper foil) that is attached to an insulating film. Therefore, also in this case, due to restrictions such as one resulting from lead thinning by side etching, there is a certain limit in increasing the number of pins.
In view of the above, the present assignee has already proposed semiconductor packages of an ultra-many-pin structure in which a semiconductor chip is bonded to a novel lead frame (or lead frame structural body).
FIG. 2 is a side sectional view showing an example of such semiconductor packages of an ultra-many-pin structure.
In the illustrated configuration of a semiconductor package 60, a plurality of electrode pads 62 are formed on the front surface (chip bottom surface as viewed in FIG. 2) of a semiconductor chip 61 along its periphery. A reinforcement plate 63 is provided outside the semiconductor chip 61 so as to surround it, and the reinforcement plate 63 defines a package external shape. A wiring film 65 is laminated on the reinforcement plate 63 through an insulating bonding layer 64. The wiring film 65 is constituted of a plurality of leads 66 consisting of inner leads 66a and outer leads 66b and an insulating film 67 which covers and protects the outer leads 66b. The tips of the inner leads 66a are connected to the electrode pads 62 formed on the chip front surface, and solder balls (external connection terminals) 68 are formed on the outer leads 66b so as to penetrate through the insulating film 67. A peripheral space of the semiconductor chip 61 is charged with a sealing resin 69, and a radiation plate 71 is bonded to the chip back surface and the reinforcement plate 63 through a heat conductive adhesive 70.
Now, a manufacturing procedure of the above semiconductor package 60 will be described roughly.
First, to produce a lead frame, a metal base 72 of a three-layer structure is prepared as shown in FIG. 3A. The metal base 72 has a structure in which an aluminum film 74 is formed on the front surface of a substrate (hereinafter called a copper substrate) 73 made of copper or a copper alloy and a nickel film 75 is formed thereon. Then, as shown in FIG. 3B, a plurality of leads 66 are formed on the front surface of the metal base 72 by electrolytic copper plating. Then, as shown in FIG. 3C, slits 76 are formed to define a lead frame outer shape for each chip. Then, as shown in FIG. 3D, an insulating film 67 is laid on the leads 66, to form a wiring film 65 constituted of the plurality of leads 66 and the insulating film 67. At this time, the lead portions projecting from the insulating film 67 become inner leads 66a and the lead portions covered with and protected by the insulating film 67 become outer leads 66b. Subsequently, as shown in FIG. 3E, an undercoat film of nickel, for instance, is formed on the outer leads 66b which are covered with the insulating film 67, and a solder material 68a is laid on the undercoat film by electrolytic plating. At this time point, the solder material 68a has mushroom shapes.
Thereafter, as shown in FIGS. 4A and 4B, the copper substrate 73, the aluminum film 74, and the nickel film 75 of the metal base 72 are sequentially removed by selective etching while an outer ring 77 is left, so that the respective leads 66 are separated from and made independent of each other. Then, as shown in FIG. 4C, a reinforcement plate 63 is bonded to the surfaces of the outer leads 66b which are covered with the insulating film 67 through an insulting bonding layer 64. Then, as shown in FIG. 4D, bumps 78 are formed on the tips of the respective inner leads 66a extending from the insulating film 67.
Thus, a lead frame 79 before attachment of a semiconductor chip is completed.
Thereafter, to attach a semiconductor chip to the above-produced lead frame 79, the tips of the inner leads 66a are connected to electrode pads 62 of a semiconductor chip 61 through the bumps 78 as shown in FIG. 5A. Subsequently, as shown in FIG. 5B, a sealing resin 69 is injected into a peripheral space of the semiconductor chip 61 and then cured. Then, as shown in FIG. 5C, a radiation plate 71 is bonded to the back surface of the semiconductor. chip 61 and the reinforcement plate 63 through a heat conductive adhesive 70. Then, as shown in FIG. 5D, the solder material 68a which was laid by electrolytic plating in the previous lead frame manufacturing process is shaped by causing it to reflow, to obtain desired solder balls 68. Finally, as shown in FIG. 5E, the outer ring 77 is separated with the outer circumference of the reinforcement plate 63 as the boundary, to complete the semiconductor package 60 shown in FIG. 2.
The semiconductor package 60 realizes an ultra-many-pin structure beyond the previous limit, because the leads 66 can be patterned more finely, which results from the fact that the leads 66 are formed on the metal base 72 by electrolytic copper plating at the stage of manufacturing the lead frame 79. Further, the semiconductor package 60 is superior in heat dissipation because the radiation plate 71 is bonded to the chip back surface side.
However, even the above ultra-many-pin structure semiconductor package 60 has the following problems:
(1) Stress-induced breakage likely occurs in the bonding portion between the chip front surface and the sealing resin 69.
(2) The front surface of the semiconductor chip 61 is likely affected by radiations such as xcex1-rays. As a countermeasure, it is necessary to coat polyimide or the like on the chip front surface.
(3) It takes time to charge the peripheral space of the semiconductor chip 61 with the sealing resin 69.
(4) Crosstalk noise likely occurs when the pattern of the leads 66 is made finer.
(5) The bumps 78 are polluted with a gas generated from the insulating bonding layer 64 when the bumps 78 are formed on the tips of the inner leads 66a in the lead frame manufacturing process.
(6) Since the solder balls 68 are obtained by shaping the mushroom-shaped solder members 68a, which are laid by electrolytic plating in the lead frame manufacturing process, into a ball shape by the reflow method immediately before the package is completed, the surfaces of the solder members 68a are oxidized during a period of time that elapses between the above two time points. Therefore, brushing is needed to eliminate oxide films prior to the reflowing of the solder members 68a. There is a possibility that the brushing causes pieces of the solder members 68a to fall off or the wiring film 65 to peel off the bonding layer 64.
FIG. 6 is a side sectional view showing another example of the semiconductor packages of an ultra-many-pin structure that have been proposed by the present assignee.
As shown in FIG. 6, a semiconductor chip 162 is disposed inside an outer ring 161. A plurality of electrode pads 163 are formed on the front surface of the semiconductor chip 162 along its periphery. A film circuit 165 is placed on and fixed to, via a bonding layer 164, a central portion of the chip front surface which excludes the pad forming region. The film circuit 165 consists of an insulating film 166 as a base and lead patterns 167 that are formed within the insulating film 166. Further, external connection terminals (solder balls) 168 are provided on the film circuit 165 at positions corresponding to the ends of the respective lead patterns 167. Leads 169 extending from the lead patterns 167 come out of the film circuit 165, and lead tips 169a are connected to the electrode pads 163 on the chip surface. A sealing resin 170 fills in the space between the outer ring 161 and the structure made up of the semiconductor chip 162, the bonding layer 164, and.the film circuit 165.
In the semiconductor package having the above configuration, the lead patterns 167 including the leads 169 of the film circuit 165 are formed by electrolytic plating that uses a metal base (not shown), and the external connection terminals 169 are formed on the lead patterns 167 also by electrolytic plating. Thus, this semiconductor package realizes a many-pin structure in which the number of pins is beyond the limit so far existed. Further, part of the metal base is left as the outer ring 161, which constitutes the package outer frame. Therefore, the positional accuracy between the package outer frame and the external connection terminals 168 is assured, which enables easy execution of an alignment operation during package mounting. In addition, what is called a CSP (chip size package) structure is attained in which the package size is made at the same level as the chip size.
In the semiconductor package shown in FIG. 6, a ground (GND) line or a power line of a printed wiring board for package mounting (hereinafter referred to as a package mounting board) is connected to an electrode pad 163 of the semiconductor chip 162 via a given external connection terminal 168 and a corresponding lead pattern 167. However, for a certain signal to be processed, there may occur a case that the power line potential or the ground potential becomes unstable. It is desired that the semiconductor package be improved in this respect.
The present invention has been made to solve the above problems, and a first object of the invention is to provide a semiconductor package which can avoid stress-induced breakage in the bonding portion on the chip front surface, can suppress the influence of radiations, and enables high-speed sealing.
A second object of the invention is to provide a semiconductor package which can reduce crosstalk noise.
A third object of the invention is to provide a manufacturing method of a lead frame which allows formation of high-quality bumps on the tips of inner leads.
A fourth object of the invention is to provide a manufacturing method of a lead frame which makes it unnecessary to perform brushing in causing a reflow of a solder material that has been laid on leads by electrolytic plating.
A fifth object of the invention is to provide a semiconductor package of an ultra-many-pin structure which enables a ground line or a power line to be connected from a package mounting board to an electrode pad of a semiconductor chip in a stable manner.
According to the invention, there is provided a semiconductor package comprising a semiconductor chip having a plurality of electrode pads formed on a peripheral portion of a front surface of the semiconductor chip and an effective device region occupying an inside of the peripheral portion; an insulating, thick-film protective layer laminated on the effective device region of the semiconductor chip; a plurality of leads constituted of outer leads and inner leads being integral with and extending from the outer leads, the inner leads having tips being connected to the electrode pads of the semiconductor chip; an insulating film for protecting the outer leads; external connection terminals formed on the outer leads; a reinforcement plate provided so as to surround the semiconductor chip; and a sealing resin for filling in a peripheral space of the semiconductor chip.
In the semiconductor package having the above configuration, since the thick-film protective layer is laminated on the effective device region of the semiconductor chip, the influence of radiations can be suppressed by the shielding effect of the thick-film protective layer even without subjecting the chip front surface to any coating treatment. Further, since the interposition of the thick-film protective layer reduces the space to be charged with the sealing resin, the resin sealing time can be shortened as much. Further, since the front surface of the semiconductor chip is covered with the thick-film protective layer rather than a sealing resin, stress-induced breakage can be prevented from occurring in the bonding portion on the chip front surface.
Further, according to the invention, there is provided a semiconductor package comprising a semiconductor chip having a plurality of electrode pads formed on a peripheral portion of a front surface of the semiconductor chip; a plurality of leads constituted of outer leads and inner leads being integral with and extending from the outer leads, the inner leads having tips being connected to the electrode pads of the semiconductor chip; an insulating film for protecting surfaces on one side of the outer leads; external connection terminals formed on the outer leads; a conductive reinforcement plate provided so as to surround the semiconductor chip, and bonded to surfaces on the other side of the outer leads through an insulating adhesive layer; a conductive outer ring provided so as to surround the reinforcement plate, and electrically connected to at least one of the outer leads; and a conductive paste for filling in a space between the reinforcement plate and the outer ring.
In the semiconductor package having the above configuration, by electrically connecting the outer ring to at least one of the outer leads, say, a grounding outer lead, the grounding outer lead and the reinforcement plate are electrically connected to each other via the outer ring. Thus, a microstrip structure is realized in which the insulating bonding layer (dielectric) is interposed between the plurality of leads (strip conductors) and the reinforcement plate (grounding plane), whereby crosstalk noise can be reduced.
Further, according to the invention, there is provided a manufacturing method of a lead frame, comprising the steps of forming a plurality of leads on a surface of a metal base of a laminated structure by metal plating; separating the plurality of leads from each other by selectively removing the metal base by etching; and forming bumps on tips of the respective separated leads, and then bonding a reinforcement plate to lead surfaces excluding bump forming regions thereof.
In the above lead frame manufacturing method, since the bumps are formed before the reinforcement plate is bonded to the lead surfaces, the bumps are never polluted by a gas generated from a bonding layer for bonding of the reinforcement plate.
Further, according to the invention, there is provided a manufacturing method of a lead frame, comprising the steps of forming a plurality of leads on a surface of a metal base of a laminated structure by metal plating; covering given regions of the leads with an insulating film; and laying a solder material on the leads at given positions by electrolytic plating with the insulating film used as a mask, and, immediately thereafter, shaping the solder material into ball shapes by reflowing.
In the above lead frame manufacturing method, since the solder material is shaped into balls by reflowing immediately after it is laid on the leads at the given positions by electrolytic plating, there occurs almost no oxidation of the solder material over time. Therefore, it is not necessary to perform brushing prior to the reflowing.
According to another aspect of the invention, there is provided a semiconductor package comprising a conductive outer ring; a semiconductor chip having a plurality of electrode pads on a peripheral portion of a front surface of the semiconductor chip and disposed inside the conductive outer ring; a film circuit disposed and formed on the side of the front surface of the semiconductor chip; a plurality of external connection terminals formed on the film circuit so as to project therefrom; first leads for electrically connecting part of the electrode pads formed on the semiconductor chip to part of the external connection terminals formed on the film circuit; a second lead for electrically connecting a grounding or power supply electrode pad among the electrode pads formed on the semiconductor chip to the outer ring; a third lead for electrically connecting a grounding or power supply external connection terminal among the external connection terminals formed on the film circuit to the outer ring; and a conductive stage bonded to a back surface of the semiconductor chip and the outer ring through respective conductive bonding layers.
In the semiconductor package having the above configuration, the grounding or power supply electrode pad is short-circuited with the chip back surface via the second lead, the outer ring, and the conductive stage, and the grounding or power supply external connection terminal is short-circuited with the chip back surface via the third lead, the outer ring, and the conductive stage. As a result, the chip back surface serves as the common ground or power supply, and the outer ring and the conductive stage that are connected to the chip back surface have the same potential. Therefore, a grounding line or a power line from a package mounting board can be connected to the electrode pad of the semiconductor chip in a more stable manner.